In its most basic form, a scan-chain is a series of elements linked together so that an output of one element is linked to an input of the next element in the series, which in turn has an output linked to an input of a subsequent element, and so on. Sometimes, circuit designers use scan-chains to provide test access to internal elements of a processor that would be otherwise inaccessible. By using a scan chain, a test engineer can shift data into a processor sequentially, using a single input port. The processor operates on the data, and the results of the operations are then read out sequentially using a single output port. In this way a maximum amount of internal circuitry can be tested with a minimum of additional complexity.
This ease of testing, however, gives rise to data access issues that must be taken into consideration, especially in light of the encryption and security requirements of the software, telecommunications, entertainment, and other industries. For example, the telecommunications industry has a need to have secure codes stored in some of the semiconductor chips used to process information in mobile phones, pagers, and the like. These secure codes may be used as part of proprietary data processing methods, for hardware identification and authentication, to specify a secure state, or for any number of other purposes. However, if the circuitry responsible for handling these codes is accessible via a scan chain, competitors might be able to exploit the scan chain to gain access to the secure codes stored in the chip or to enter a secure state.
In order to address the problem of exploiting the scan chain to gain access to secure information stored in the chip or to fool the chip into thinking it is in a secure state, manufacturers have generally removed circuitry used to process secure information from the scan chain. By removing this circuitry from the scan chain, it becomes more difficult for unauthorized users to gain access to the secure codes. However, this solution leaves a significant portion of the chip unable to be completely tested.
As should be apparent from the above discussion, currently available testing methodologies are less than ideal, in that they force a designer to choose either test access with decreased data security, or data security without test access for significant portions of a data processor. What is needed is some way to permit test access to portions of a processor that process secure information, but maintaining the secrecy of any secure information in the processor.